Integrated circuits are often designed to incorporate scan test circuitry that facilitates testing for various internal fault conditions. Such scan test circuitry typically comprises scan chains comprising multiple scan cells. The scan cells may be implemented, by way of example, utilizing respective flip-flops. The scan cells of a given scan chain may be configured to form a serial shift register for applying test patterns at inputs to combinational logic of the integrated circuit. The scan cells of the given scan chain are also used to capture combinational logic outputs responsive to applied test patterns.
In one exemplary arrangement, an integrated circuit with scan test circuitry may have a scan shift mode of operation and a functional mode of operation. A flag may be used to indicate whether the integrated circuit is in scan shift mode or functional mode. In the scan shift mode, the flip-flops of the scan chain are configured as a serial shift register. A test pattern is then shifted into the serial shift register formed by the flip-flops of the scan chain. Once the desired test pattern has been shifted in, the scan shift mode is disabled and the integrated circuit is placed in its functional mode. Internal combinational logic results occurring during this functional mode of operation are then captured by the chain of scan flip-flops. The integrated circuit is then once again placed in its scan shift mode of operation, in order to allow the captured combinational logic results to be shifted out of the serial shift register formed by the scan flip-flops, as a new test pattern is being scanned in. This process is repeated until all desired test patterns have been applied to the integrated circuit.
Many scan chains also incorporate lockup latches. For example, in scan chains that have multiple clock domains, lockup latches are commonly utilized to ensure that scan shift timing requirements are met at transitions between the clock domains. However, movement of scan cells during integrated circuit design can cause design verification complications in relation to positioning of the lockup latches. Also, conventional lockup latches can consume significant amounts of power outside of the scan shift mode of operation.